This release brings in a new improved wishbone interface to the Xilinx Spartan-6 MCB.
This new interface provides better compatibility with pipelined Wishbone and improved performance.
Although the user interface remains the same, because of the complete rewrite, this new version has been tagged as v2.0.0 to make users aware of the fact that there is a big underlying change.
A new SystemVerilog testbench is provided which tests the DDR controller by performing write/read-back tests of various lengths.
For a full list of changes, see the changelog.