This release brings in a new improved L2P DMA master implementation (for performing DMA transfers from the device to the host). This new implementation provides better compatibility with pipelined Wishbone, improved performance and a number of important fixes for corner cases.
This release also introduces a SystemVerilog testbench that exercises most of the features and corner cases of the gn4124-core.
Although the user interface remains the same, because of the complete rewrite, this new version has been tagged as v3.0.0 to make users aware of the fact that there is a big underlying change.
For a full list of changes, see the changelog.