- as you mentioned,
you can set it directly in VHDL via port wrs_tx_cfg_i of board module
Is this a harded -coded way to set the mac address?
If so, I think the mac address is fixed, and can’t be changed during the running time.
Not at all. Generics would have been used if it was to be hardcoded. It is an input signal and it can be changed. However, the change should be done while there is no transmission requested (i.e. no valid data is provided and the tx_dreq_o is HIGH).
There is a scientific part connected to the Streamers in our design, and it will send data to different. destinations,so we need the dst mac address to be changed by our software when the system is running.
Sure, you can use this input signal to change the dst mac.
So maybe it’s better to set appropriate register in WB registers connected to AUX WB Master.
You can also use the WB register configuration. In both cases, you need to make sure that no data is sent during the reconfiguration of dst mac. If the transmission is triggered in HDL, you might need to use the input signal instead of WB registers. Note that both methods of setting dst mac (input signal and WB register) modify the same input register that is used when creating the Ethernet frame. If this internal register is modified during creating of Ethernet Header, the header will be corrupted. If you use WB registers to set this internal register while the transmission of data via WR Streamers is triggered inside HDL, it is near impossible to ensure the reconfiguration is done between transmissions. In such case, it is much better to use the input signal (wrs_tx_cfg_i) and implement in HDL a process which ensures the reconfiguration is done between transmissions.
I got the information from the user’s manual(wrpc-v4.2), and I think it gives the example of spec_wr_ref design.
However, WRPC internal memory is at 0x00000, not 0x40000.
Is there anything wrong with it?
Apologies, you are correct. Me bad. The reference design of BTrain-over-WhiteRabbit uses 0x40000 for WRPC. However, the reference design of wrpc in wr-cores uses 0x00000, just as you said.
However, we use our own hardware platform, which is based on kintex-7, and it doesn’t have a PCIe or VME bridge.
So I think we can’t use the software…
Unless you extend it to use whatever bus you use internally
- one more question
what’s the difference between pipelined WB and classic WB?
I searched it on google, and got less detailed information about it…
I think it’s best to refer to the WBv4 spec and the BLOCK transactions
- pdf page 49 for classic/standard
- pdf page 51 for pipelined
In short, in pipelined WB, you do not wait for ack before reading/writing the consecutive word
BTW. could you tell me why you think the WR Streamers are not good for your application (the other post you made to white-rabbit-dev list)?