Having two DDR3 memories will complicate the PCB design and increase the cost.
Would it be possible to stream the data from an FMC mezzanine straight to the PCIe bus (the 2-lane Gen2 gives 1 GByte/sec bandwidth).
Or could one use the internal FPGA memory + a DMA controller send data to the processor memory?
Both options would make that one would not need the DDR3 connected to the FPGA core.
Suggestion made by Joe.