xwb_sdb_crossbar User Guide

  1. Is there a user guide for xwb_sdb_crossbar? I would like to understand how to control this block.
  2. I would like to ask you if you have a user guide for xwb_sdb_crossbar. I would like to know how I can send data from slave_i(0) to master_o(0), for instance. In other words, how can I send a message from slave_i to specific master_o port.
  3. Do you know if xwb_sdb_crossbar support both single and pipelined read and writes?
  1. Unfortunately I don’t recall we had any manual/user guide for this core
  2. You can have a look at the WR PTP Core VHDL for an example how modules can be connected through the crossbar and how to define the addressing layout (base addresses) for WB slaves (https://ohwr.org/project/wr-cores/blob/proposed_master/modules/wrc_core/wr_core.vhd)
  3. Yes, it works both with WB classic and pipelined modes. I think also block read/writes should work fine as the crossbar keeps wb slave locked to a requesting master throughout the whole duration of CYC.


Hi Orlando, I’ll just add here for the sake of completeness the reply that I had given you by email, before suggesting that we move the discussion to the new forum.

The xwb_sdb_crossbar is used in numerous projects, so you can easily learn by example. Here’s one:


Essentially, you need to pass the memory map of your peripherals to the “g_layout” generic of the crossbar. In the example above, this is done at line 662.

The c_INTERCONNECT_LAYOUT is a constant that is built between lines 233 and 324. Have a look at it and feel free to ask specific questions about things you do not understand.

Once everything has been declared and assigned to the crossbar generic, then it’s just a matter of making a Wishbone read/write with the correct address. In the example above, if the slave_i(0) port receives a read request for address 0x1308, it will forward it as a read request for master_o(3), at address 0x08.

Hi Dimitris,

Thank you very much! For some reason, I’ve forgot your explanation. Sorry for that. I will base on it to design the testbench.

Thank you.

Thank you very much for your explanation, @greg.daniluk !